Digital integrated circuit (IC) devices that interface to high-speed memory interfaces typically receive data and strobe clocks simultaneously. In order to ensure timing and guarantee data-capture, the incoming clocks need to be phase adjusted, usually by 90 degrees. A phase detector is a device whose output represents the phase difference between the two oscillating input signals. A reference signal is applied as one input, and the phase or frequency modulated signal is applied to the other input. The phase detector takes the two inputs and generates an output signal that comprises a signal that is proportional to the phase difference between the two inputs.
A delay-locked loop (DLL) is a digital circuit that employs phase detection to change the phase of a clock signal, usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits (such as DRAM devices). DLLs can also be used for clock recovery. A DLL effectively functions as a negative-delay gate placed in the clock path of a digital circuit. A DLL compares the phase of one of its outputs to the input clock to generate an error signal which is then integrated and fed back as the control to all of the delay elements. A DLL is built around a delay chain composed of a number of delay gates connected in series. The input of the chain is connected to the clock that is to be delayed. A multiplexer is connected to each stage of the delay chain, and a selector of the multiplexer is automatically updated by a control circuit to produce the delay effect. The output of the DLL is the resulting, delayed clock signal. The phase shift can be specified either in absolute terms (in delay chain gate units), or as a proportion of the clock period, or both.
Conventional phase detectors for use in DLL and similar phase-locked loop (PLL) devices are usually configured to detect 90 degree and 180 degree phase differences between two clock signals. Such phase detectors typically cannot efficiently detect other phase differences, such as 270 degree or 540 degree phase differences. As clock speeds increase, such as in present 5 GHz applications, the number of components in the delay chain also increases. The DLL monitors and controls the clocking of these components. The short clock periods and number of devices can increase timing variations due to effects such as process variations, supply voltage variations, temperature and other environmental effects (collectively, the “PVT” effect). In general, a delay of only 90 degrees is often too short a period of time to accommodate all of the delay elements that are to be regulated. That is, accommodating all of the delay elements in order to have a constant delay across the PVT range may result in a total delay that is larger than 90 degrees.
What is desirable, therefore, is a phase detector that can detect greater than 90 or 180 degrees.
What is further desirable is a phase detector that can detect substantially 270 degree and 540 degree phase differences between two clock signals.